Notes-for-CAIE

1.4 Processor Fundamental

1.4.1 CPU architecture

• show understanding of the basic Von Neumann model for a computer system and the stored program concept
• show understanding of the roles carried out by registers, including the difference between general purpose and special purpose registers: Program Counter, Memory Data Register, Memory Address Register, Index Register, Current Instruction Register and Status Register
• show understanding of the roles carried out by the Arithmetic and Logic Unit (ALU), Control Unit and system clock
• show understanding of how data are transferred between various components of the computer system using the address bus, data bus and control bus
• show understanding of how the bus width and clock speed are factors that contribute to the performance of the computer system
• show understanding of the need for ports, for example Universal Serial Bus (USB), to provide the connection to peripheral devices

Buses

• Address bus: transmits an address between the processor and memory. (One way)
• Data bus: carries data between the processor and memory. (Two way)
• Control Bus: transmits signals between the control unit and the other components. (Two way)

Bus width: determines the no. of bits that can be simultaneously transferred [1]

Greater bus width, significant increase in the number of directly addressed memory locations [1]

Clock speed: (MHz/GHz) the no. of cycles that are performed by the CPU per second. [1]

Faster clock speed means more operations executed per unit of time [1]
however faster clock speed causes processor to heat up [1]

Clock tick = Clock cycle

Clock rate: (MHz/GHz) the speed at which a micro-processor execute instructions

Registers

Abbr.	Full Name	Function
MAR	Memory address register	stores the address of location for read/write operation
MDR	Memory data register	stores the data involved in read/write operation
PC	Program counter	contains the location of the instruction that is to be executed next.
ACC	Accumulator	(single general-purpose register) stores the result of arithmetic and logic operations performed by the processor
CIR	Current instruction register	holds the instruction that is to be executed
SR	Status Register	interpreted as independent bits; Each bit is set depending on an event

Explain what is meant by register

s18 11 Q8 [2]

• Small piece of memory
• Part of the processor
• Temporary storage of data

MDR

s18 11 Q8 [2]

• Stores data when fetched from memory
• Stores data that is being written to memory
• The location accessed is the address held in MAR

Units

| Abbr. | Full Name | Function | |:——|:————————–|:———————————————| | ALU | Arithmetic and Logic Unit | Performs arithmetic and logical operations | | CU | Control Unit | send and receive signals; control operations |

Benefits of using USB [2]

• It’s nearly impossible to wrongly connect a device
• supported by many operating systems
• automatically detected and configures when attached
• has became a industrial standard

1.4.2 The fetch-execute cycle

• describe the stages of the fetch-execute cycle
• show understanding of ‘register transfer’ notation
• describe how interrupts are handled

Fetch-execute (FE) cycle

1. MAR <- [ PC ]
2. PC <- PC + 1
3. [ MDR ] <- [ [ MAR ] ]
4. [ CIR ] <- [ MDR ]

How special purpose register are used in the fetch stage of fetch-execute cycle

s16 11 Q3 [4]

1. PC holds the address of the next instruction to be fetched
2. The address in the PC is copied to the MAR
3. PC is incremented
4. The instruction is copied to MDR from the address held in MAR
5. The instruction from MDR copied to the CIR

The purpose of the double brackets, e.g. [ [ MAR ] ]

The content of the address pointed by MAR is transferred to the MDR

How to read content

1. MAR -> address
2. Read signal is sent by processor to memory
3. content -> MDR

How to write content

1. content -> MDR
2. address -> MAR
3. Write signal sent by processor to memory
4. Content is changed

Interrupt

w18 13 Q6 [2]

• A signal from a source
• Telling the processor its attraction is needed

How fetch-execute cycle handles an interrupt

s16 11 [4] At the end of the cycle for the current instruction the processor checks if there is an interrupt.
If the interrupt flag is set, the register contents are saved,
the address of the Interrupt Service Routine (ISR) is loaded to the Program Counter (PC)
and when the ISR completes, the processor restores the register contents.

1.4.3 The processor’s instruction set

show understanding that the set of instructions are grouped into instructions for:

• data movement (register to main memory and vice versa)
• input and output of data
• arithmetic operations
• unconditional and conditional jump instructions
• compare instructions
• modes of addressing: immediate, direct, indirect, indexed, relative (No particular instruction set will be expected but candidates should be familiar with the type of

Relative addressing: The offset is added to the base address to give the actual address
Indexed addressing: The content of the Index register is added to operand to give the actual address

1.4.4 Assembly Language

• show understanding of the relationship between assembly language and machine code, including symbolic and absolute addressing, directives and macros
• describe the different stages of the assembly process for a ‘two-pass’ assembler for a given simple assembly language program
• trace a given simple assembly language program

macro (subroutine): contains a sequence of instructions that can be used more than once in a program
directives: an instruction that tells the assembler to do something

Two-pass assembler

1st Pass

1. Data items are converted into their binary equivalent
2. Any directives are acted upon
3. Any symbolic address are added to the symbolic address table

2nd Pass

1. Forward references are resolved
2. Any symbolic address is replaced by an absolute address

How the assembler made entries to the symbol table

w17 13 Q4 [3]

• The assembler scans the assembly language instructions in sequence
• When it meets a symbolic address checks to see if already in symbol table
• If not, it adds it to the symbol table in the symbolic address column
• If it is already in symbol table check if absolute address known
• If the absolute address is known, it is entered in the appropriate cell
• If the absolute address is not known mark / leave as unknown